1. Field of the Invention
The present invention relates to a data processing system provided with control devices such as a CPU and ASIC, and freely detachable storage devices such as font cards.
2. Description of the Prior Art
Conventional data processing systems provided with a CPU include a program ROM for storing control programs used by the CPU to execute prescribed control processes; data ROM for storing data to be referenced during those control processes: RAM that serves as a work area during those control processes for performing input and output of data: I/O interface for executing in hardware data input and output between external devices; and the like.
Each of these storage devices contains storage space that can be accessed by the CPU. Addresses are assigned for the storage spaces of each storage device such that the addresses do not overlap. The CPU can access each of the storage devices by outputting the relevant address data.
However, the storage space contained in individual storage devices is generally smaller than the total address space that can be accessed by the CPU. Therefore. an address decoder is normally positioned between the CPU and the storage devices. The address decoder executes processes to generate the address of each storage device based on address data outputted from the CPU.
Occasionally, the width of the I/O data bus used by the CPU is different from that of the data bus for the storage devices. Therefore, some conventional systems employ a configuration in which a plurality of storage devices are arranged together and made to conform to the I/O data width of the CPU using the address decoder.
For example, a 32-bit CPU has a 32-bit data bus. However, the data buses in the program ROM and data ROM currently have a maximum width of 16 bits. Hence, conventional systems have used the two ROM devices together to form a 32-bit data bus width.
In addition to program ROM and other storage devices that are preinstalled in the data processing system, there are other storage devices called card ROM, such as font cards and the like, which are detachably inserted in the data processing system. These card ROM are designed to suit the CPU data bus width of the data processing system that uses such card ROM. For example, a data processing system such as a printer system provided with a 32-bit CPU uses font cards having a data bus width of 16 bits.
Accordingly, the CPU of the printer system cannot easily read the font card simply by mounting the font card in the card connection section provided in the printer system. Rather, a process is performed to read 16 bits of data from the card twice in one read cycle.
However, some types of card ROM such as the font card mentioned above require that read accesses are performed by accessing a prescribed area of the total address area and by reading 8 bits or 16 bits of data per read cycle.
In addition, some types of CPU are,capable of writing data to storage devices at 8, 16, or 32 bits, but can only read data from such storage devices in units of 32 bits. This is particularly common in cache memory provided in the CPU.
Hence, if a card ROM requiring data to be read at 16 bits by accessing a restricted portion of address area is used in a data processing system provided with a CPU that can only read data in units of 32 bits, it is not possible to read data from the prescribed portion of memory when performing two reads in one read cycle.
In view of the foregoing, it is an object of the present invention to provide a data processing system capable of reliably reading data from a part of memory, even when a storage device that requires data to be read at a data bus width smaller than the width of the system data base is used in a data processing system provided with a CPU that can only read data at the maximum data bus width of the system.
This and other objects of the present Invention will be attained by a data processing system including a data processing device for reading process data from an external device at a first bit width; a connection device for connecting the data processing device with a storage device when the storage device is mounted in the connection device. wherein the storage device is detachably mounted and has a reduced bus size with which process data is read at a second bit width that is smaller than the first bit width; and an address specifying data control device for outputting via the connection device at least a portion of data specifying an address for a storage area in the storage device, based on prescribed instruction data from the data processing device.
The data processing device includes an address specifying data output device for outputting data that specifies an address of a standard storage area, in which at least process data of the first bit width is stored within the storage device; an valid process data extraction device for extracting valid process data of the second bit width based on process data read at the first bit width corresponding to data specifying an address, when specifying an address in the standard storage area equivalent to an area of the reduced bus size, and a partial storage area selection device for selecting a desired partial storage area in the standard storage area equivalent to an area of the reduced bus size in which data of the second bit width is stored, and outputs selection instruction data.
With this construction, the address specifying data control device generates at least one part of the data for specifying the address of a partial storage area based on the selection instruction area and outputs the address to the storage device via the connection device With this construction, when the address specifying data output device of the data processing device specifies the address of a standard storage area corresponding to a reduced bus size area and in which process data of the first bit width is stored, the partial storage area selection device selects a desired partial storage area in the standard storage area In which data of the second bit width is stored, and outputs selection instruction data to the address specifying data control device. Based on this selection instruction data. the address specifying data control device generates at least one portion of data for specifying the address of the partial storage area and outputs that address data to the storage device mounted in the connection device.
Regardless of the address in the storage device that the data processing device specifies with address specifying data, a partial storage area storing data of the second bit width is selected and data of the partial storage area is output. Since the second bit width is smaller than the first bit width, output of the second bit width is performed a plurality of times to form the equivalent of the first bit width. The valid process data extraction device of the data processing device extracts valid process data of the second bit width based on process data read at the first bit width. Hence, data of the second bit width is included a plurality of times within data read at the first bit width. However, since only the valid portion of the second bit width is extracted, in effect an appropriate read at the second bit width is achieved.
In another aspect of the invention, the selection instruction data includes data specifying a portion of the address for the partial storage area.
With this construction. the partial storage area selection device outputs selection instruction data that includes data specifying a portion of the address for the partial storage area. Hence. a special address specification corresponding to a specific bit width need not be specified using address specifying data of the data processing device, even when the storage device mounted in the connection device requires that data for a specific area be read at a specific bit width. As a result. it is possible to minimize the changes to software.
In another aspect of the invention. the selection specifying data includes data for specifying the second bit width.
With this construction, the partial storage area selection device outputs selection instruction data including data for specifying the second bit width. Accordingly. even when the data processing device outputs fixed address specifying data. the low-order address equivalent to the second bit width changes each time a read is performed on the storage device. Hence, even when the second bit width of the storage device changes according to the address area, an access can be performed at an appropriate address corresponding to the second bit width set at each area.
In another aspect of the invention, the first bit width is a multiple of the second bit width. The address specifying data control device generates address data at a bit number capable of expressing the multiple value, and outputs this address data to an address bus of the storage device via the connection device.
With this construction, the address specifying data control device generates address data based on the selection instruction data. However, this address data includes a bit number that can express the multiple value of second bit widths necessary to form the first bit width Hence, it is possible to reliably obtain data of the first bit width by reading data at the second bit width a number of times equivalent to the multiple value. As a result. the system can guarantee a reliable data read, even when the data processing device can only perform reads at the first bit width.
In another aspect of the invention, the address specifying data control device generates at least a portion of the data for specifying the address of the partial storage area based on the selection instruction data and data specifying either an even or odd address, and outputs the data to the storage device via the connection device.
With this construction, the address specifying data control device generates and outputs at least a portion of the data for specifying the address of the partial storage area based on selection instruction data. However, in addition to this address data, the address specifying data control device also generates data specifying either an even or an odd address and outputs this data to the storage device via the connection device. Hence, it is possible to reliably read data at the second bit width without changing the hardware configuration, even when the second bit width required for the storage device covers a plurality of values.